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rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. op97 low power, high precision operational amplifier features low supply current: 600 a max op07 type performance offset voltage: 20 v max offset voltage drift: 0.6 v/ c max very low bias current 25 c: 100 pa max ?5 c to +125 c: 250 pa max high common-mode rejection: 114 db min extended industrial temperature range: ?0 c to +85 c pin connections 8-lead pdip (p suffix) 8-lead soic (s suffix) 1 2 3 4 8 7 6 5 op97 null over comp out v+ null ?n +in v general description the op97 is a low power alternative to the industry-standard op07 precision amplifier. the op97 maintains the standards of performance set by the op07 while utilizing only 600 a supply current, less than 1/6 that of an op07. offset voltage is an ultralow 25 v, and drift over temperature is below 0.6 v/ c. external offset trimming is not required in the majority of circuits. improvements have been made over op07 specifications in several areas. notable is bias current, which remains below 250 pa over the full military temperature range. the op97 is ideal for use in precision long-term integrators or sample-and-hold circuits that must operate at elevated temperatures. common-mode rejection and power supply rejection are also improved with the op97, at 114 db minimum over wider ranges of common-mode or supply voltage. outstanding psr, a supply range specified from 2.25 v to 20 v and the op97? minimal power requirements combine to make the op97 a preferred device for portable and battery-powered instruments. the op97 conforms to the op07 pinout, with the null potenti- ometer connected between pins 1 and 8 with the wiper to v+. the op97 will upgrade circuit designs using 725, op05, op07, op12, and 1012 type amplifiers. it may replace 741-type ampli- fiers in circuits without nulling or where the nulling circuitry has been removed.
rev. e e2e op97especifications (@ v s = 15 v, v cm = 0 v, t a = 25 c, unless otherwise noted.) op97e op97f parameter symbol conditions min typ max min typ max unit input offset voltage v os 10 25 30 75 v long-term offset voltage stability v os /time 0.3 0.3 v/month input offset current i os 30 100 30 150 pa input bias current i b 30 100 30 150 pa input noise voltage e n p-p 0.1 hz to 10 hz 0.5 0.5 v p-p input noise voltage density e n f o = 10 hz 1 17 30 17 30 nv/ hz hz hz hz hz hz hz h h
rev. e op97 e3e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the op97 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 v input voltage 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 v differential input voltage 3 . . . . . . . . . . . . . . . . . . . . . . . . 1 v differential input current 3 . . . . . . . . . . . . . . . . . . . . 10 ma output short-circuit duration . . . . . . . . . . . . . . . . indefinite operating temperature range op97e, op97f (p, s) . . . . . . . . . . . . . . . . . e40 c to +85 c storage temperature range . . . . . . . . . . . . e65 c to +150 c junction temperature range . . . . . . . . . . . . e65 c to +150 c lead temperature (soldering, 60 sec) . . . . . . . . . . . . . 300 c package type ja 4 jc unit 8-lead pdip (p) 103 43 c/w 8-lead soic (s) 158 43 c/w notes 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 for supply voltages less than 20 v, the absolute maximum input voltage is equal to the supply voltage. 3 the op97?s inputs are protected by back-to-back diodes. current-limiting resis- tors are not used in order to achieve low noise. differential input voltages greater than 1 v will cause excessive current to flow through the input protection diodes unless limiting resistance is used. 4 ja is specified for worst-case mounting conditions, i.e., ja is specified for device in socket for pdip package; ja is specified for device soldered to printed circuit board for soic package. ordering guide temperature package package model range description option * op97ep e40 c to +85 c 8-lead pdip n-8 op97fp e40 c to +85 c 8-lead pdip n-8 op97fs e40 c to +85 c 8-lead soic r-8 op97fs-reel e40 c to +85 c 8-lead soic r-8 op97fs-reel7 e40 c to +85 c 8-lead soic r-8 * for outline information, see package information section.
rev. e ? op97?ypical performance characteristics input offset voltage ( v) number of units 0 ?0 100 200 300 400 ?0 0 20 40 1894 units v s = 15v t a = 25 c v cm = 0v tpc 1. typical distribution of input offset voltage temperature ( c) input current (pa) ?0 ?5 ?5 0 25 50 ?0 75 t a = 25 c v cm = 0v i b i os i b + ?0 ?0 0 20 40 60 100 125 tpc 4. input bias, offset current vs. temperature source resistance ( ) effective offset voltage ( v) 1000 1 1k 100 10 3k 10k 30k 100k 1m 300k 3m 10m balanced or unbalanced v s = 15v v cm = 0v ?5 c t a +125 c t a = 25 c tpc 7. effective offset volt- age vs. source resistance input bias current (pa) number of units 0 ?00 100 200 300 400 ?0 0 50 100 1920 units v s = 15v t a = 25 c v cm = 0v tpc 2. typical distribution of input bias current common-mode voltage (v) input current (pa) ?0 ?5 ? 0 5 10 ?0 15 t a = 25 c v s = 15v i b i os i b + ?0 ?0 0 20 40 60 tpc 5. input bias, offset current vs. common-mode voltage source resistance ( ) effective offset voltage drift ( v/ c) 100 0.1 1k 10 1 10k 100k 1m 10m balanced or unbalanced v s = 15v v cm = 0v 100m tpc 8. effective tcv os vs. source resistance input offset current (pa) number of units 0 ?0 100 200 300 400 ?0 0 20 40 1894 units v s = 15v t a = 25 c v cm = 0v ?0 60 500 tpc 3. typical distribution of input offset current time after power applied (minutes) deviation from final value ( v) 0 0 1 2 3 4 234 5 t a = 25 c v s = 15v v cm = 0v 1 5 j packages z, p packages tpc 6. input offset voltage warm-up drift time from output short (minutes) short-circuit current (ma) ?0 0 ?5 ?0 ? 10 20 123 0 15 5 v s = 15v output shorted to ground t a = +125 c t a = +25 c t a = ?5 c t a = +125 c t a = +25 c t a = ?5 c tpc 9. short-circuit current vs. time, temperature
rev. e op97 ? supply voltage (v) supply current ( a) 300 0 325 375 400 450 5 no load t a = +125 c t a = ?5 c t a = +25 c 350 425 10 15 20 tpc 10. supply current vs. supply voltage load resistance (k ) open-loop gain (v/mv) 10000 1 1000 100 2510 20 t a = +125 c t a = ?5 c t a = +25 c v s = 15v v o = 10v tpc 13. open-loop gain vs. load resistance output voltage (v) differential input voltage (10 v/div) ?5 ? 0 5 10 r l = 10k v s = 15v v cm = 0v ?0 15 t a = +125 c t a = ?5 c t a = +25 c tpc 16. open-loop gain linearity frequency (hz) common-mode rejection (db) 0 1 100 10 100 1k 10k t a = 25 c v s = 15v v cm = 10v 20 40 60 80 120 140 100k 1m tpc 11. common-mode rejection vs. frequency frequency (hz) 100 1 10 1 10 100 1000 current noise 1/f corner 120hz voltage noise 1/f corner 2.5hz t a = 25 c v s = 2v to 20v 1000 voltage noise density (nv/ hz) current noise density (fa/ hz ) 100 10 1 1000 tpc 14. noise density vs. frequency load resistance ( ) output swing (v p-p) 35 1 10 30 10k 1k 100 t a = 25 c v s = 15v a vcl = +1 1% thd f o = 1khz 25 20 15 10 5 tpc 17. maximum output swing vs. load resistance frequency (hz) power-supply rejection (db) 20 0.1 40 60 80 100 10 100 1k 10k ?sr t a = 25 c v s = 15v v s = 10v p? 1 100k 140 + psr 120 1m tpc 12. power-supply rejection vs. frequency source resistance ( ) 10 0.01 10 2 1 0.1 t a = 25 c v s = 2v to 20v total noise density ( v/ hz ) resistor noise 1khz 10hz r r r s = 2r 10 3 10 4 10 5 10 6 10 7 10 8 1khz 10hz tpc 15. total noise density vs. source resistance frequency (hz) output swing (v p-p) 35 1 30 100k 1k 100 t a = 25 c v s = 15v a vcl = 1 1% thd r l = 10k 25 20 15 10 5 10k tpc 18. maximum output swing vs. frequency
rev. e ? op97 frequency (hz) open-loop gain (db) 80 ?0 100 60 10m 1k 100k 40 10k 1m ?0 ?0 0 20 phase phase shift (degrees) 225 180 135 90 t a = +125 c t a = ?5 c t a = ?5 c t a = +125 c v s = 15v c l = 20pf r l = 1m 100pf overcompensation gain v s = 15v c l = 20pf r l = 1m 100pf overcompensation tpc 19. open-loop gain, phase vs. frequency (c oc = 0 pf) frequency (hz) open-loop gain (db) 80 ?0 100 60 10m 1k 100k 40 10k 1m ?0 ?0 0 20 phase phase shift (degrees) 225 180 135 90 t a = +125 c t a = ?5 c gain v s = 15v c l = 20pf r l = 1m 100pf overcompensation t a = ?5 c t a = +125 c tpc 22. open-loop gain, phase vs. frequency (c oc = 100 pf) frequency (hz) open-loop gain (db) 80 ?0 100 60 10m 1k 100k 40 10k 1m ?0 ?0 0 20 phase phase shift (degrees) 225 180 135 90 t a = ?5 c t a = +25 c t a = +125 c gain v s = 15v c l = 20pf r l = 1m 100pf overcompensation t a = ?5 c t a = +125 c tpc 25. open-loop gain, phase vs. frequency (c oc = 1000 pf) frequency (hz) thd + n (%) 0.0001 10 10k 1k 100 t a = 25 c v s = 15v r l = 10k 1% thd v out = 3v rms a vcl = 100 a vcl = 10 a vcl = 1 0.001 0.01 0.1 1 10 tpc 20. total harmonic distortion plus noise vs. frequency overcompensation capacitor (pf) 0.1 1 0.01 0.001 10 100 10000 1 slew rate (v/ s) r l = 10k v s = 15v c l = 100pf t a = +125 c t a = ?5 c 1000 tpc 23. slew rate vs. overcompensation frequency (hz) open-loop gain (db) 80 ?0 100 60 10m 1k 100k 40 10k 1m ?0 ?0 0 20 phase phase shift (degrees) 225 180 135 90 t a = ?5 c t a = +25 c t a = +125 c gain v s = 15v c l = 20pf r l = 1m 100pf overcompensation t a = +125 c t a = ?5 c tpc 26. open-loop gain, phase vs. frequency (c oc = 10,000 pf) load capacitance (pf) overshoot (%) 70 0 10 60 10000 1000 100 t a = 25 c v s = 15v a vcl = +1 v out = 100mv p-p c oc = 0pf 50 40 30 20 10 +edge ?dge tpc 21. small signal overshoot vs. capacitive load overcompensation capacitor (pf) 100 1 10 1 10 100 10000 1000 gain bandwidth (khz) v s = 15v c l = 20pf r l = 1m a v = 100 t a = ?5 c 1000 t a = +125 c tpc 24. gain bandwidth product vs. overcompensation frequency (hz) output impedance ( ) 0.001 10 100 1k 10k t a = 25 c v s = 15v 1 a vcl = 1000 100k a vcl = 1 0.01 0.1 1 10 100 1000 tpc 27. closed-loop output resistance vs. frequency
rev. e op97 e7e application information the op97 is a low power alternative to the industry-standard precision op amp, the op07. the op97 may be substituted directly into op07, op77, 725, 112/312, and 1012 sockets with improved performance and/or less power dissipation and may be inserted into sockets conforming to the 741 pinout if nulling circuitry is not used. generally, nulling circuitry used with ear- lier generation amplifiers is rendered superfluous by the op97?s extremely low offset voltage and may be removed without com- promising circuit performance. extremely low bias current over the full military temperature range makes the op97 attractive for use in sample-and-hold amplifiers, peak detectors, and log amplifiers that must operate over a wide temperature range. balancing input resistances is not necessary with the op97. offset voltage and tcv os are degraded only minimally by high source resistance, even when unbalanced. the input pins of the op97 are protected against large differen tial voltage by back-to-back diodes. current-limiting resistors are not used so that low noise performance is maintained. if differ- ential voltages above 1 v are expected at the inputs, series resistors must be used to limit the current flow to a maximum of 10 ma. common-mode voltages at the inputs are not restricted and may vary over the full range of the supply voltages used. the op97 requires very little operating headroom about the supply rails and is specified for operation with supplies as low op97 r pot = 5k to 100k c oc ev +v figure 1. optional input offset voltage nulling and overcompensation circuits figure 2. small-signal transient response (c load = 100 pf, a vcl = 1) as 2 v. typically, the common-mode range extends to within 1 v of either rail. the output typically swings to within 1 v of the rails when using a 10 k load. offset nulling is achieved utilizing the same circuitry as an o p07. a potentiometer between 5 k and 100 k is connected between pins 1 and 8 with the wiper connected to the positive supply. the trim range is between 300 v and 850 v, depending upon the internal trimming of the device. ac performance the op97?s ac characteristics are highly stable over its full operating temperature range. unity-gain small-signal response is shown in figure 2. extremely tolerant of capacitive loading on the output, the op97 displays excellent response even with 1000 pf loads (figure 3). in large-signal applications, the input protection diodes effectively short the input to the output during the transients if the amplifier is connected in the usual unity- gain configuration. the output enters short-circuit current limit, with the flow going through the protection diodes. improved large-signal transient response is obtained by using a feedback resistor between the output and the inverting input. figure 4 shows the large-signal response of the op97 in unity gain with a 10 k feedback resistor. the unity-gain follower circuit is shown in figure 5. the overcompensation pin may be used to increase the phase margin of the op97 or to decrease gain-bandwidth product at gains greater than 10. figure 3. small-signal transient response (c load = 1000 pf, a vcl = 1) figure 4. large-signal transient response (a vcl = 1)
rev. e e8e op97 op97 10k v out 2 3 6 v in figure 5. unity-gain follower figure 6. small-signal transient response with over- compensation (c load = 1000 pf, a vcl = 1, c oc = 220 pf) guarding and shielding to maintain the extremely high input impedances of the op97, care must be taken in circuit board layout and manufacturing. board surfaces must be kept scrupulously clean and free of moisture. conformal coating is recommended to provide a humidity barrier. even a clean pc board can have 100 pa of leakage currents between adjacent traces, so that guard rings should be used around the inputs. guard traces are operated at a voltage close to that on the inputs, so that leakage currents become minimal. in noninverting applications, the guard ring should be connected to the common-mode voltage at the invert- ing input (pin 2). in inverting applications, both inputs remain at ground, so that the guard trace should be grounded. guard traces should be made on both sides of the circuit board. op97 2 3 6 unity-gain follower op97 2 3 6 noninverting amplifier op97 2 3 6 inverting amplifier 1 8 pdip bottom view figure 9. guard ring layout and connections op97 v out 2 3 6 i o i o digital inputs 30pf r fb pm7548 figure 7. dac output amplifier op97 r5 10k v out 2 3 6 v 1 r1 10k r2 10k r3 10k r4 10k e15v +15v 7 4 r l i l figure 8. current monitor high impedance circuitry is extremely susceptible to rf pickup, line frequency hum, and radiated noise from switching power supplies. enclosing sensitive analog sections within grounded shields is generally necessary to prevent excessive noise pickup. twisted-pair cable will aid in rejection of line frequency hum. the op97 is an excellent choice as an output amplifier for higher resolution cmos dacs. its tightly trimmed offset volt- age and minimal bias current result in virtually no degradation of linearity, even over wide temperature ranges. figure 8 shows a versatile monitor circuit that can typically sense current at any point between the 15 v supplies. this makes it ideal for sensing current in applications such as full bridge drivers where bidirectional current is associated with large common-mode voltage changes. the 114 db cmrr of the op97 makes the amplifier?s contribution to common-mode error negligible, leaving only the error due to the resistor ratio inequality. ideally, r 2/ r 4 = r 3/ r 5.
rev. e op97 e9e the digitally programmable gain amplifier shown in figure 10 has 12-bit gain resolution with 10-bit gain linearity over the range of e1 to e1024. the low bias current of the op97 main- tains this linearity, while c1 limits the noise voltage bandwidth allowing accurate measurement down to microvolt levels. digital in gain (av) 4095 e1.00024 2048 e2 1024 e4 512 e8 256 e16 128 e32 64 e64 32 e128 16 e256 8 e512 4 e1024 2 e2048 1 e4096 0o pen loop many high speed amplifiers suffer from less-than-perfect low frequency performance. a combination amplifier consisting of a high precision, slow device like the op97 and a faster device such as the op44 results in uniformly accurate performance from dc to the high frequency limit of the op44, which has a gain-bandwidth product of 23 mhz. the circuit shown in figure 11 accomplishes this, with the op44 providing high frequency amplification and the op97 operating on low fre- quency signals and providing offset correction. offset voltage and drift of the circuit are controlled by the op97. v out op97 2 3 6 0.1 f +15v c1 220pf 17 16 pm7541 v ref r fb 1 2 3 18 2.5mv to 10v range depending on gain setting v in e15v 0.1 f +15v i out 1 i out 2 0.1 f figure 10. precision programmable gain amplifier op44 v out 2 3 6 op97 2 3 6 r2 20k 5 10k 1 f r1 2k v in 0.1 f 10k 5pf r2 r1 a v = figure 11. combination high-speed, precision amplifier figure 12. combination amplifier transient response
rev. e e10e op97 outline dimensions 8-lead plastic dual in-line package [pdip] p-suffix (n-8) dimensions shown in inches and (millimeters) seating plane 0.180 (4.57) max 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 8 1 4 5 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.100 (2.54) bsc 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095aa 0.015 (0.38) min 8-lead standard small outline package [soic] narrow body s-suffix (r-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa
rev. e op97 e11e revision history location page 7/03?data sheet changed from rev. d to rev. e. deleted h-08a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal deleted q-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal deleted e-20a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal deleted die characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 deleted wafer test limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 updated tpc 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1/02?data sheet changed from rev. c to rev. d. edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 deleted dice characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 deleted wafer test limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
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